Computer Architecture and Organization

We live in the information age today. Computing has changed most aspects of our lives, personal as well as professional. How has this revolution come about? From embedded computers in everyday devices, to personal devices like smart-phones, to high end server machines and super-computers, what are the principles underlying computer design? What has helped us achieve fast and cheap computing today, in all these devices? This course answers these questions, through a combination of theory and practical lab exercises.


Chapter 1: Introduction
What is Computer Architecture? What is a computer? IC technology behind the computing revolution.
a. Introduction to Computer Architecture
b. Parts of a Computer
c. IC Technology
Chapter 2: The Hardware-Software Interface
Instruction set as the language of a computer, its design, instruction encoding, instruction support for HLL features
a. Instruction Set Design
b. Instruction Encoding
c. Function Call Support
d. HLL Code to Process
e. Arithmetic in MIPS
Chapter 3: Computer Performance Quantification
Performance quantification: the basis of an engineer's approach to computer design
Chapter 4: Single Cycle Implementation of MIPS
Hardware implementation of an instruction set: the MIPS single cycle implementation
a. Hardware Implementation Preliminaries
b. Single Cycle Implementation of MIPS ISA (Subset)
c. Extending the Single Cycle MIPS Implementation
d. Analysis of the Single Cycle MIPS Implementation
Chapter 5: Multi-Cycle Implementation Of MIPS
Hardware implementation of an instruction set: the MIPS multi-cycle implementation, working toward a pipelined implementation
a. Multi Cycle Implementation of MIPS ISA (Subset)
b. Control logic for the multi-cycle MIPS implementation
c. Extending the Multi-Cycle MIPS Implementation
d. Handling exceptions
Chapter 6: Pipelining
Pipelining the hardware implementation for efficiency, pipelining hazards and ways to mitigate them, exceptions in a pipeline
a. Introduction to pipelining
b. Structural Hazards, Pipelined Datapath
c. Data Hazards in the Pipeline
d. Control Hazards in the Pipeline
e. Pipeline Control
f. Exceptions in the Pipeline
Chapter 7: Memory Systems: Cache Memory
The memory system as a hierarchy of caches, cache design, cache performance
a. One System to Know Them All
b. The Memory System: A Hierarchy of Caches
c. Cache Design: A Beginning
d. Associative Caches
e. Cache Performance Analysis
f. Program Performance Analysis in Presence of Cache
Chapter 8: Memory Systems: Cache Memory
Virtual memory magic in practice: what, why, how? Hardware and OS support for VM management
a. Virtual Memory
b. Virtual Memory and Caches
c. Hardware and OS Interaction for Virtual Memory
Chapter 9: Input/Output Systems
Input/output systems, disks, bus systems
a. Input/Output Systems: An Introduction
b. Magnetic Hard Disk Technology
c. RAID: Redundant Array of Inexpensive Disks
d. Hamming Codes
e. Introduction to Buses
f. Bus Interfacing
g. Bus Protocols
h. Bus Arbitration
i. Hardware and OS Interaction for IO
Chapter 10: Conclusion
What to remember 5 years hence, 10 years hence?

Hands-On Labs

1. MIPS assembly programming in the SPIM simulator
2. Functions in MIPS assembly, calling conventions
3. Recursive functions in MIPS assembly, understanding stack frame manipulations
4. SPIM exception handler
5. Using gcc to generate MIPS code, answering performance questions using measurements
6. Understanding pipeline hazards and stalls using the WinMIPS64 pipeline simulator
7. Data forwarding in the pipeline, code scheduling, loop unrolling
8. Understanding and analysing cache performance using the dineroIV cache simulator
9. Writing a program to guess a computer’s cache size
10. Understanding hard-disk geometry using a program
C/C++, Data Structures (for labs)
Estimated Time
50 hours (theory), 30 hours (hands-on labs)

Meet the instructor

Cinque Terre
Bhaskaran Raman
Bhaskaran Raman received his B.Tech in Computer Science and Engineering from Indian Institute of Technology, Madras in May 1997. He received his M.S. and Ph.D. in Computer Science from University of California, Berkeley, in 1999 and 2002 respectively. He was a faculty in the CSE department at Indian Institute of Technology, Kanpur (India) from June 2003. Since July 2007, he is a faculty at the CSE department at Indian Institute of Technology, Bombay (India).

His research interests and expertise are in communication networks, wireless/mobile networks, and technology for education. His current focus and specific interests are mobile crowdsensing, WiFi performance diagnosis, and use of technology in large classrooms for effective teaching.